(a) Field of the Invention
The invention relates to a memory processing device, particularly to a memory control system and a method to read data from memory.
(b) Description of the Related Art
In general, a microprocessor (MCU), has no build-in read-only memory (ROM), and in the past the microprocessor usually reads the ROM code from an externally coupled read-only memory (such as: flash memory) via a parallel bus. Since the current design trend is to integrate the microprocessor and scaler into a single chip, in order to reduce the pin count of the microprocessor, a serial bus is utilized to read the ROM code from the read-only memory. Under the serial bus structure, the microprocessor can only read a single bit of the data within one clock cycle of base band when accessing the ROM code from the read-only memory. Therefore, the processing speed of the microprocessor is seriously reduced.
For example, FIG. 1 illustrates the waveform diagram of a two-period (2T) microprocessor operating in serial transmission mode. In FIG. 1, the label “MCUclk” indicates the processing clock of the microprocessor and the label “xclk” indicates the clock of the system base band. In general, the 2T microprocessor fetches one byte of data from the read-only memory during the first period T0 of the MCUclk. However, in order to fetch eight bits of data, the 2T microprocessor must firstly spend time to decode an eight-bit command and a twenty-four-bit address so that the 2T microprocessor can execute the data (ROM code) during the second period T1 of the MCUclk. As shown in the figure, when fetching and executing the ROM code, the 2T microprocessor needs to spend forty base band clocks xclk to complete each operation, that is, the 2T microprocessor needs eighty base band clocks xclk to complete fetching and executing one byte of data. In general, one command of a microprocessor needs one to four bytes of data. Taking a two-byte command as an example, a 2T microprocessor needs four MCUclks, that is, one hundred and sixty xclks to complete the operation. Therefore, under the serial transmission structure, the time needed for various microprocessors (2T, 6T, 8T MCU, and so forth) to execute a command is greatly extended and the program executing speed of the overall system is limited.